16 Bit Vedic Arithmatic& Logic Unit

Abstract

This paintings is devoted for the format and FPGA implementation of a 16bit Arithmeticmodule, which makes use of Vedic Mathematics algorithms.For arithmetic Multiplication severa Vedic multiplication techniques like UrdhvaTiryakbhyam,Nikhilam and Anurupye has been very well analysed. Also Karatsubaalgorithmformultiplication has been mentioned.It has been determined that UrdhvaTiryakbhyamSutrais most green Sutra (Algorithm), giving minimumdelayformultiplication of alltypes of numbers.UsingUrdhvaTiryakbhyam, a 16x16 bit Multiplier has been designed and the use of this Multiplier, a Logic unit unit and Shifter has been designed. Then, an Arithmetic and proper judgment  module has been designed which employs those Vedic multiplier Operation and addition, subtraction,shifter and common sense gates. Logic verification of those modules has beendone via the use of Xilinx10.Three. Further, the complete format of Arithmetic module has been realised on Xilinx Spartan 3E FPGA bundle deal and the output has been demonstrated.The synthesis effects display that the computation time for calculating the made of 16x16 bits is 24.28 ns,at the same time as for the whole  ALU operation 38.313 ns.