Pulse Triggered Flip Flop using Conditional Feedthrough Scheme for Low Power Applications

Abstract

In this paper, an efficient conditional feedback through pulse triggered flip flop is adopted. Pulse-triggered FF (P-FF) is a single-latch structure which is more popular than the conventional transmission gate (TG) and master–slave based FFs in high-speed applications. By introducing a shared power generator and an output feedback controlled conditional keeper, consumed power is minimized and the floating nature of the internal node is vanished respectively. The proposed work is implemented and simulated in CADENCE VIRTUOSO CMOS 180nm technology. The performance of the proposed method has advantages of power and power- delay-product measurements. This design has become as a new alternative for high-efficient sequential circuits in high-speed applications.