ASIC Implementation of Random Perturbation Algorithm for Neural Network Application

Abstract

An Analog VLSI Implementation of an on-chip learning neural network is described in this paper. The network considered comprises an analog feed forward network with digital weights and update circuitry. The chip consists of a comparator, incrementer and decrementer circuit to update the weights. The training algorithm used is Random Perturbation Algorithm. From experimental results it is seen that the weights are updated as per the algorithm. Intense simulations were carried out in HSPICE simulation tool using 0.18µm technology to verify its functioning.