Performance comparison of Array Multiplier with Wallace Multiplier using Reversible Logic Structure

Authors

  • Subba Rao P, Satya Sindhu P, Durga Naga Lakshmi N

Abstract

Over the past few years, research in reversible logic multipliers has done very efficiently to reduce the partial product number. The power and speed of the logic design is efficiently utilized by using reversible Array Multiplier. Array multiplier is an important design in VLSI because, Multiplication involves key role in Arithmetic and Logical operations. From recent years the research has going on multipliers to improve performance in various factors. Here, an array multiplier that produces less delay and efficient power utilisation is proposed using reversible half adder and multiplexer based reversible full adders. By this design the combinational path delay and chip area are decreased.A Wallace multiplier is also developed using the same reversible logic and their power and path delay are calculated to achieve high efficiency. The entire design is developed in Verilog HDL and the software used is XILINX ISE 14.5.

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Published

2020-05-10

Issue

Section

Articles