Design of Low Power Hybrid Model for Scan based VLSI Testing

Abstract

In CMOS technology, the DFT based VLSI Testing becomes more expensive and power consuming; these are the main challenging issues in testing. In this paper, to overcome power issues in scan based testing a hybrid model of testing is presented and the model includes scan masking, scan re-ordering, selective scan cell triggering concepts together in a single roof. The experimental results are presented for ISCAS 89 bench mark circuits.