Design of a Clock Distribution Network using Combined Programmable, Swallow Counters and Low Power Prescaler
In this paper we have showed the design of the clock distribution network using 2/3 frequency divider. In wireless communication applications such as WLAN, ZIGBEE, Bluetooth, etc.. frequency synthesizer is the main component. The speed of the frequency synthesizer depends on the pre-scale oscillator and controlled voltage. 2/3 prescaler must implement using TSPC (True single phase clock) or ETSPC (True single phase clock) and slippers. In this article we propose pre-scaler with the integration of two NOR gates in both phases of pre-scaler design instead of using an AND gate and an OR gate. The two designs are compared in terms of power. Using the proposed prescaler, we have designed a clock distribution network that can be shared by 2,3,4,5,32,33,47,48 etc. prescaler implemented with 180nm technology can reach 5Ghz frequency. This system also focuses on combining programmable and swallow counters. Clock distribution network code written in verilog, modeled using Xilinx and Modelsim.