Design and Performance Analysis of Single Precision Floating Point Multiplier Using Parallel Prefix Adders

Abstract

This paper presents single precision floating point (32-bit) multiplier design using Parallel Prefix algorithm and Radix-4 Booth algorithm. Parallel prefix adders such as Kogge-Stone and Han-Carlson adders are implemented by parallel prefix algorithm is used to perform the partial product addition in the multiplication operation and this adder is also used in the exponent addition in the multiplier design. Radix-4 Booth algorithm is used to reduce the multiplier bits so that the number of partial products generation can be reduced significantly. The simulation results of single precision floating point multiplier designed using Kogge-Stone and Han-Carlson adder implementations are compared. The multiplier is designed using Tanner EDA 13.0 tool in 130nm CMOS technology.