Power Optimized BCD adder Using Low Power Techniques

Abstract

Today growing market demands the Microelectronic Circuits with less power consumption because of mobile and portable electronic systems are working with the Batteries. In this scenario, density of the chip increases with the increase of transistors on the chip. Increase of density causes difficult of reducing the power dissipation and hence limit the functioning of the system. In this work proposed BCD adder circuit by  Gating-Vdd technique to reduce the power consumption and analyze the proposed  adder circuit with Sleep Transistor and Conventional techniques. Today most of the VLSI systems are having  CMOS devices, that’s the reason concentrated on the development of BCD adder using CMOS devices.