Design and Analysis of BIST Approach for 3D-Mesh Nocs Router Testing

Abstract

A new built-in self-test architecture for complex and heterogeneous systems on a chip is presented with flexible, hierarchical, and distributed power-restrained, embedded memory. The proposed structure consists of a BIST architecture in a 3-D NOC, low area, low power memory BIST control system, and a serial interconnection to them for low routing overheads. The architecture is technology-independent due to its simplicity; the proposed approach offers heterogeneous memories as well as the error spotting to minimize time complexity and achieve high test competitiveness in power and time constraints.