Design and Performance Evaluation of Gate-All- Around Nanowire FET at Sub-7nm Technology Node

Authors

  • D Rashi Chaudhary
  • M. W. Akram

Abstract

In the Electronics world, there is a need of more and more scaling of semiconductor devices to march at the tempo of Moore’s law so that we face less and less problems in making devices with shrunken dimensions at Nano scale. It has been found in the published literature that the GAA Nanowire FET shows favorable results as compared to the FinFET structure at the technology node beyond 10 nm. In today’s time FinFET is assumed to be the Industry Standard Semiconductor technology for making an Electronics Product. Therefore, in this work, a TCAD study of the device GAA Nanowire FET at sub-7 nm technology node is carried out. The design and investigation of the influences of varying channel length in ultra

–short nanometer regime on drain current is studied. And then we further investigate and analyze the variability in the performance trends of the device GAA NWFET at ultra-low power Drain voltage (Vds=0.05 V) by keeping the channel length, channel height and channel width constant at 5 nm scale and by varying the Channel doping concentrations, Gate Oxide thickness, Gate Oxide material and use of high–k dielectric materials in Spacer region. Further investigation of the influence of ultra-nanowire channel radius less than or equal to 3nm on device conductivity.

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Published

2020-01-21

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Section

Articles