Design of a Highly Reliable Multiphase Frequency Generator Based Adder
For a large System-On-A-Chip (SOC), the manufacturing process is limited primarily by the manufacturing process of the Silicon Intellectual Property (SIP) adopted by the SOC. If the manufacturing process of each SIP were more flexible, then the difficulty and time in exploiting an SOC could be reduced. The Adder circuit is basically required in many applications like DSP (digital signal processing) architecture, Microprocessor, Microcontroller, Filter designing and data Processing units. As the multi-phase over-sampling reception and transmission, plenty of sampling circuits adopting relatively low sampling rates to achieve high transmission rates. Therefore, the operating clock speed of the chip can be effectively reduced such that the limit on the manufacturing process can be lowered. From many years researchers are trying to make small size devices with high operating speed. Therefore design of highly reliable multiphase frequency generator based adder is presented in this paper. In this paper firstly different adders are studied. Then the design steps of multiphase frequency generator based adder are described. Performance analysis of area and delay is performed in Xilinx ISE 14.7 using Verilog code.