EXTREME VMIN CMOS DESIGN USING D FLIP-FLOP

Abstract

D flip-flop based on a high current pass transistor. On Comparing flip-flop has a very high Imax with Standard CMOS circuits operating at very minimum voltage supply. The semi floating gate synchronized with capacitive coupling gives a current at max level as output. This mechanism with floating capacitance helps in boosting current such flip-flops are used in any Vmin digital CMOS circuits. The delay is reduced compared to a conventional sense around fourteen percentage. The simulated data provided is obtained using mixed-signal systems with MATLAB and Simulink and Taiwan Semiconductor Company produced 0.13 µm bipolar-CMOS process. Our proposed model can be used in any digital based low voltage CMOS applications.