Hardware Implementation of Polar Codes for very Short Length Messages

Abstract

An emerging error-detection and correcting technique developed in the recent years is Polar codes applicable in next generation wireless communications. This coding technique does not focus on randomization of the bits like other techniques does as it is based channel polarization and achieves almost Shannon Capacity also. This paper presents a successive cancellation (SC) algorithm based FPGA implementation of Polar codes for very short length messages of 8 bits. The implementation focuses on low complexity decoder for high speed applications and is to be extended for variable length like 32,128,256,512 bits to access the hardware complexity and design aspects for further implementation.  Simulation results show the performance of polar codes the scope being that these codes outperform compared to LDPC and Turbo codes in wireless applications.