Real Time Parallel Architecture in VLSI using Microcontroller

Abstract

Abstract- This paper proposes a novel architecture for high speed arithmetic by a “multiplier-and-accumulator (MAC)”. A hybrid type of CSA is developed by the combination of multiplication and accumulation. The largest delay accumulator in MAC that are merged into CSA and evaluation of overall performance.The CSA trees proposed here use a “1’s-complement-based radix-2 modified Booth’s algorithm (MBA)” and the array is modified for extending sign for increasing operand’s bit density. The carry is propagated to LSBs of partial products by CSA and LSB is generated for decreasing final adder’s input bits. The intermediary results are accumulated in proposed MAC resulting in carry and sum bits instead of final adder output, which makes optimization of pipeline scheme for improving performance. The synthesis of architecture proposed here was done using standard CMOS library of 90,130,180 and 250 nm. The results are analysed based on experimental and theoretical estimation such as delay, pipelining scheme and hardware resources. The delay modelling use Sakurai’s alpha power law. The MAC proposed here is superior in properties in comparison with standard design and it has twice performance at same clock frequency as previous research and it could be applied to high performance requirements.