Design of Parallel Pipelined DIF- FFT Architecture

Abstract

To compute the Discrete Fourier Transform a formal procedure for designing FFT architectures using folding transformation and register minimization technique. This research work presents a new approach to develop parallel pipelined 128 points Radix2³ Real Fast Fourier Transform (RFFT) and Complex Fast Fourier Transform (CFFT) architecture. The area, frequency, throughput, delay and power consumption can be reduced in the parallel pipelined by using RFFT & CFFT architecture.  The power and area consumption can be reduced in parallel pipelined by using RFFT & CFFT architecture. The output samples are obtained, to a desired order to implement on XILINX Virtex-4Xc4vfx12 FPGA